{
 "generated": "2026-11-02",
 "node": {
  "id": "org:renesas",
  "type": "Organization",
  "name": "Renesas（瑞萨）",
  "org_type": "Developer",
  "kind": "company",
  "homepage": "https://www.renesas.com/",
  "aliases": [
   "Renesas",
   "瑞萨"
  ],
  "entry": "agent",
  "by": "landscape-facts",
  "at": "2026-11-01T15:20:38Z",
  "degree": 0.0011,
  "n_apps": 0,
  "n_models": 0
 },
 "page": "https://xiaopingfeng.com/graph/e/org/renesas/",
 "out": [],
 "in": [
  {
   "type": "supplies_to",
   "sentence": "Cadence向Renesas供应产品或服务",
   "direction": "in",
   "id": "org:cadence",
   "name": "Cadence",
   "note": "Verisium：R-Car 车规设计实测 debug 生产力最高提升 6 倍、仿真探测性能提升 2 倍；Cerebrus 卡另写 Renesas 实测总负时序裕量（TNS）改善 75%",
   "product": "Verisium 与 Cerebrus",
   "status": "agent",
   "evidence": [
    {
     "kind": "own",
     "label": "本站页面",
     "text": "Landscape「芯片设计全流程」第 04 层「功能验证与仿真」的卡片「Cadence Verisium」：Renesas在R-Car车规设计上实测debug生产力提升最高6倍",
     "url": "https://xiaopingfeng.com/graph/e/layer/chip-design-flow--4/#player-cadence-verisium"
    }
   ]
  }
 ]
}